This invention relates generally to lead frames for use in integrated circuit packaging and more particularly, a lead frame having one or more layered conductive planes thereon is described.
Referring to FIG. 1, a conventional lead frame 10 generally includes a die pad 17, die pad support arms 15 and leads 11 having lead tips 12 which circumscribe the die. In the manufacture of conventional lead frames the die pad 17, support arms 15 and long leads 11 and lead tips 12 are typically formed from a single metal strip. The lead forming step may be either an etching process or a stamping process. In these processes the areas between the leads 11 are removed through either stamping or etching. The area between the leads 11 and the lead tips 12 are usually referred to as slots 14. In the etching process, a mask of the pattern of leads, die pad and support arms is laid over a metal strip. The exposed areas are then etched away creating the slots 14 between the leads. The stamping process usually consists of stamping out the slots 14 between the leads, die pad 17 and support arms 15. Multiple stamp tool punches, shaped in the form of the respective slots 14, punch out the slots 14.
The support arms 15 extend out from the die pad to support the die pad during handling. An integrated circuit is placed on the die pad 17, in the center of the lead frame 10. After the leads 11, die pad 17 and support arms 15 are formed, the lead frame 10 may be annealed to strengthen and relieve stress on the leads and support arms. This may be followed by plating the lead tips 12 with an electrically conductive material. Plating also allows for better bonding to the bonding wires when the leads are connected to the integrated circuit.
The leads may then be taped with an adhesive strip to keep the leads from moving during handling. The adhesive strip may be a single picture frame style strip that is placed across the leads. An alternative is the application of separate strips placed across a set of leads. The former process allows for better tolerances when the tape either shrinks or expands causing the leads to move. Then, the lead frame 10 may be trimmed to free the lead tips 12 from the die pad 17.
After trimming, the lead frame is ready to be packaged. An integrated circuit is placed on the die pad 17 and bonded to the lead tips 12 with bonding wires. The inner portion of the lead frame 20 is then encapsulated with an encapsulating material. The excess metal that supported the entire lead frame 22 is then trimmed away to free the long leads 11 from each other. The end product is a packaged semiconductor device.
A current problem with conventional lead frames is the frequency response of the leads. The length of the leads introduce inductance in the power and ground leads. The longer the ground and power leads the greater the inductance. The inductance in turn increases the amount of power consumption in a semiconductor package. The length also make the power and ground leads susceptible to noise from neighboring leads. The increased inductance makes the lead frame and the connected integrated circuit susceptible to power surges and drops. The inductance hampers efforts to reduce internal and external noise. Decoupling capacitors applied across the ground and power pins are often used to alleviate these problems. The decoupling capacitors help to filter out noise from the power supply and neighboring devices as well as protect against sudden power surges and drops. Semiconductor packages having a large number of pins may require two to three decoupling capacitors. The capacitors are a significant cost in products utilizing large integrated circuits.
Ideally, the frequency response of the power and ground leads should be a low pass filter. By decreasing the inductance in the power and ground leads and increasing the capacitance between the power and ground leads a better frequency response can be obtained. The improved frequency response will allow a semiconductor package to operate at high speeds. Also, the impedance of the leads are reduced which decreases power consumption.
U.S. Pat. No. 4,891,687 to Mallik et al., discloses the use of a multilayer molded plastic integrated circuit package to obtain a compact package which had the side benefit of reducing inductance and increasing capacitance in the power and ground leads. Mallik teaches the use of a pair of intricate conducting layers with specialized tabs that are bonded to the leads of an otherwise ordinary lead frame that does not include a die pad. The specialized tabs taught in Mallik also requires that the conductive layers be precisely attached to the lead frame so the tabs align with particular leads on the lead frame. The tabs must then be bonded using relatively expensive non-standard bonding techniques. Mallik also requires that the integrated circuit be placed directly on the lower conductive layer.